State of the art technologies such as mobile telephones, laptop and notebook computers, and hand-held communication devices, among others, have been improved and made more user-friendly in terms of weight and cost reductions by advances in microelectronic circuit design and materials that provide faster computing speeds with lower power demands. Product performance requirements spiral from the effects of increasing operating speed, decreasing package size, lowering cost, and reducing time to market. These spiraling requirements raise new component packaging and handling issues in which the circuit advances must be complemented by circuit packaging to take full advantage of the technology improvements. Packaging must protect the chip against adverse environmental conditions and dissipate the tremendous amount of heat produced, yet maintaining the electrical integrity.
Quad flat packages (QFPs) are surface mount packages that have been developed to implement the miniaturization and advanced functions of various kinds of electronic devices. QFPs come in a number of different forms including packages with leads extending out from all the four sides of the package body and package without leads, known as QFNs (quad flat package—no leads). A QFP in particular facilitates impedance matching because it has a substantially square contour, i.e., all wiring in the package has substantially the same length. For this reason, QFPs are extensively applied to, among others, logic circuits needing high-speed performance.
Most QFNs and QFPs are plastic and are not hermetic. The plastic is typically molded around the circuit, so there is no cavity. Hermeticity is desirable to prolong circuit life. Cavities are needed with certain types of circuits because their components cannot tolerate physical contact with the package material. This is particularly true for MEMS (Micro ElectroMechanical System) devices, which include electrical and mechanical components integrated on the same substrate, for example, a silicon substrate. Further, in addition to the fact that plastic packages incorporate materials that are not permitted by military specifications, plastic packages usually do not meet the military leak rate specifications of 1×10−7 standard cubic centimeters of helium gas per second. There are known methods for forming ceramic QFNs and QFPs from multi-layered co-fired ceramic, however, the start-up costs of a fabrication facility can be prohibitive. In particular, co-fire methods have been developed using BeO and AlN, however, they have not been widely adopted because the ceramic material must be high purity, and high purity ceramics are not readily sintered in a multi-layer process such that very high process temperatures are required.
U.S. Pat. No. 5,616,954 describes a flat package for semiconductor integrated circuits that includes a cavity and is hermetically sealed. This package provides versatility in accommodating different chips, relieves the need to use leads for circuit ground and improves electrical shielding. The process for fabricating this package utilizes a multi-layer, multi-step approach.
A single layer surface mount package is disclosed in U.S. Pat. No. 6,639,305, on which the present inventor is named as a co-inventor. This SLSMP provides a number of advantages over the prior art, but the use of a lead frame makes it difficult to achieve the miniaturization required in many QFP applications. Further, the alloy base has relatively poor thermal conductivity and therefore may not provide the most efficient thermal performance.
The need remains for a small surface mount package that is formed from ceramic for hermeticity to provide high reliability while conforming to the dimensional requirements of conventional QFPs, and further that is economical to manufacture.